The invention generally relates to electronic amplifiers and, more particularly, the invention relates to a circuit for reducing the sensitivity of an output stage due to environmental and/or fabrication process effects.
Power amplifiers are used to drive heavy loads in a wide variety of applications. Many such applications use output stages, such as class-AB output stages, to achieve high linearity and efficiency. A number of factors affect the performance of the output stage. Among others, the quiescent current (i.e., no AC signal) of the output stage affects performance of the amplifier primarily through crossover distortion, power dissipation, and stability. To ensure reliable operation, the quiescent current of the output stage should be independent of supply, temperature, and process variations.
Many prior art output stages, however, are sensitive to such process variations. For example, many output stages are designed to operate at a very low power, thus requiring very small currents. Accordingly, a small variation in the quiescent current can adversely affect the overall performance of the power amplifier. It thus is important for the quiescent current in the output stage to be constant and thus, relatively independent of external factors, such as those noted above.
In accordance with one aspect of the invention, a circuit for matching a first mirror transistor with a second mirror transistor in a current mirror includes a bias transistor and a diode connected transistor to match such mirror transistors. More particularly, the circuit is a part of an amplifier having an output with a quiescent voltage and at least one rail voltage. The first mirror transistor has a first terminal coupled to the output, and a second terminal coupled to the at least one rail voltage. To effectuate its mirroring function, the bias transistor is coupled to a first terminal of the second mirror transistor, and the diode connected transistor is coupled to both a second terminal of the second mirror transistor and the at least one rail voltage. The bias transistor has a terminal with a quiescent voltage that is substantially equal to the quiescent voltage of the output.
In illustrative embodiments, the transistors are one of field effect transistors and bipolar junction transistors. If bipolar junction transistors, the transistors may be at least one of NPN bipolar junction transistors and PNP bipolar junction transistors. Also if bipolar junction transistors, the bias transistor and the diode connected transistor at least in part cause the first and second mirror transistors to have substantially equal collector-emitter quiescent voltages.
The first mirror transistor may be an output transistor. Moreover, the terminal of the bias transistor (i.e., the terminal having a quiescent voltage that is substantially equal to the quiescent voltage of the output) illustratively is not coupled with the output.
In accordance with another aspect of the invention, a circuit for matching a first mirror transistor with a second mirror transistor in a current mirror includes a first bias transistor and a second bias transistor to provide proper mirroring. More specifically, the first mirror transistor is a diode connected transistor, and the first bias transistor is coupled with a first terminal of the second mirror transistor. The second bias transistor is coupled with a second terminal of the second mirror transistor. The second bias transistor also is a diode connected transistor. The first bias transistor, second bias transistor, and second mirror transistor form a voltage loop in which the sum of the voltages in the loop equals zero.
In a manner similar to other aspects of the invention, the transistors are one of field effect transistors and bipolar junction transistors. If bipolar junction transistors, the transistors may be at least one of NPN bipolar junction transistors and PNP bipolar junction transistors. Also if bipolar junction transistors, the first and second bias transistors at least in part cause the first and second mirror transistors to have substantially equal collector-emitter quiescent voltages. Additionally, the first bias transistor may have a base node, and the second bias transistor also may have a base node. The base nodes of the two bias transistors are coupled at the same potential.
In accordance with other aspects of the invention, an amplifier (having an output with a quiescent voltage and at least one rail voltage) has an output transistor that receives a controlled current from a mirroring arrangement. To that end, the output transistor has a first terminal coupled with the output and a second terminal coupled with the at least one rail voltage. The amplifier also includes a first bias transistor forming a mirror with the output transistor, a second bias transistor coupled to a first terminal of the first bias transistor and having a terminal with a quiescent voltage that is substantially equal to the quiescent voltage of the output, and a third bias transistor coupled to both a second terminal of the first bias transistor and the at least one rail voltage. The third bias transistor illustratively is a diode connected transistor. The amplifier also includes a mirror transistor that forms a mirror with the third bias transistor, a fourth bias transistor coupled with a first terminal of the mirror transistor, and a fifth bias transistor coupled with a second terminal of the mirror transistor. The fifth bias transistor is a diode connected transistor, and the fourth bias transistor, fifth bias transistor, and mirror transistor form a voltage loop in which the sum of the voltages in the loop equals zero.
In a manner similar to other aspects of the invention, the transistors can be one of field effect transistors and different types of bipolar junction transistors. Additionally, the output transistor may be a portion of an A-B output stage. The second bias transistor illustratively is doped in an opposite manner to the doping of the first bias transistor. For example, in this embodiment, if the first bias transistor is an NPN bipolar junction transistor, then the second bias transistor is a PNP bipolar junction transistor.